Original SL-C9 DCDC converter
Description Terry Magee has kindly submitted the following account of his success at managing to fix a Mk1 C9 DC to DC unit.

These units are found in the SL-C9 and provide the power for the florescent display and also the tuner.

The unit is highly prone to failure causing the florescent display to go out and the tuner to stop receiving any signals.

Circuit diagrams
Observations and Tips
  1. There was nothing wrong with the primary AC to DC converter. The circuit diagram confirmed that the "5V" supply is an unregulated rectification of a tap on the transformer supplying the regulated "12V" supply and this caused the anomalous OFF LOAD behaviour mentioned previously. Loading the "12V" rail with 2, then 3, 100 ohm 3W resistors showed excellent regulation and the "5V" rail magnitude and stability was reasonable provided:
    1. The "12V" was loaded to avoid the switched mode regulator shutting down.
    2. The "5V" was loaded with at least 100mA.
  2. The DC to DC converter drew absolutely zero current when it was removed from board "D" and tested on a 12V PSU, confirming it was faulty.
  3. One large soldering iron was not sufficient to melt the solder all around the seam and separate the converter can from its base. In the absence of a second large iron and another pair of hands, the module can be opened as follows: With the can in a rubber faced vice, very carefully file a 1.5mm strip off the bottom of both long edges of the can, where it overlaps a flange on the periphery of the base. This will allow a thin screwdriver to be carefully inserted between the can and the base and each end to be levered apart in turn after an iron has been applied to that end. A soldered butt joint, rather than overlapping joint, can still be carefully made when resealing the module.
  4. The first fault found was an open circuit emitter in the inverter transistor Q2. Its CB junction capacitance still measured around 15pF indicating that it was probably a 1A transistor, which intuitively looked reasonable (Later these Icmax and CJC figures were confirmed in an entry for 2SD774 in "Towers International Transistor Selector" book of brief outline specifications).
  5. To check that the transformer had not been damaged, I first drove its primary (collector) winding from a 50 ohm signal generator through L2 with Q2 removed and found that the winding ratios made sense for +28V and -26V outputs. For a constant I/P voltage, the secondary winding voltages also peaked at 94 kHz, in agreement with the oscillation frequency marked on the waveform diagram shown in the manual. This also clarified the purpose of L2, as the negative peak of the sine wave at the primary of T1 needs to go below ground to be large enough to develop the desired voltages at the secondaries.
  6. During this test, it was noticed that the voltage on the +38V reservoir capacitor C4, and to a lesser extent on the -26V capacitor C5, decayed rapidly between each rectified peak of these voltages. This was traced to extremely high series resistance in C4 and very high resistance in C5. All the electrolytics were then checked and ALL were found to have developed very high or extremely high series resistances, obviously due to drying out because of the high operating temperature inside this module. They were all replaced by high temperature types with low ESRs, designed for use in switched mode supplies. This fault in C4 and C8 affecting the bias feedback loop could explain the fact that these modules generally fail on power up (see comment 13) and that repairs are not always successful (e.g. if the electrolytic capacitors are not replaced at the same time, or if a high enough gain transistor is not used).
  7. I initially tried out the converter with an unbranded transistor from my junk box which had a similar collector to base capacitance CJC and a reasonable gain at Ic up to a few hundred mA. As a precaution I temporarily shorted out C8 to run Q2 on minimum base bias current and gradually increased the supply voltage with the bench PSU set to current limit at 20mA. With this transistor and minimum bias current, the circuit oscillated at about 60kHz with a peak primary voltage less than the supply voltage. A damped parasitic oscillation (at between 5 &10 MHz) was also observed at the collector of Q2, superimposed on the 60kHz waveform for part of the cycle. This occurred after the negative peak, where Ic and dIc/dt are largest and was initially thought to be due to Q2 amplification (just before it turns off) of a signal fed back by the transformer base winding (although the level of this parasitic observed on the collector and base windings was very much lower).
  8. Before carrying out any further tests, I checked the characteristics of the output regulation loop controlling the bias current to Q2. This was achieved by connecting the normal 12V supply to module pin 1, by shorting the base of Q2 to ground through a current meter, by connecting a variable bench PSU to module pin 3 and by shorting out the base of Q4 to prevent it disabling the loop (due to current through R3). This showed that the total bias through R1/Q1/R2 increased rapidly to 3.4mA by the time 0.7V is developed at the output, decreases only slowly to 2.5mA as that voltage increases to 37.5V and decreases very rapidly after that to the circa 55uA allowed by R2, as Q1 turns off. To avoid damaging the transistor, and/or the transformer, while further tests were carried out, the bias feedback loop short across C8 was reinstated and a second 0-30V bench PSU was used to inject extra bias current directly at the base of Q2 through a 22k resistor.
  9. When, by the above means, the bias to Q2 was gradually increased (using the unbranded transistor and the power supply limiting now set to 75mA), the amplitude of the oscillation progressively increased causing Q2 to go into saturation for an increasing part of the cycle and causing the frequency of the main oscillation to progressively increase from the initial 60kHz. As the transistor came out of saturation, the damped parasitic oscillation was still seen superimposed on the voltage at the collector of Q2. As the bias was further increased the current drawn started to increase disproportional to the increase in output voltage and the transistor got very very hot before enough output voltage was developed. This was found to be due to too low a gain with this transistor and to too rapid a fall off of gain at high currents (by this time I had seen an outline spec for the gain of a 2SD774 which gave 300 typical at Ic= 150mA).
  10. At first Sony said they could not supply a 2SD774 without knowing their part number for it and I could not find another supplier listing it. Eventually I got through to an engineer who found 3 different part numbers for various versions of 2SD774 included on some old documentation he had for the obsolete board "D". These numbers are: 8729-177-42 for a 2SD774-3 8729-177-43 for a 2SD774-4 and 8729-140-96 for a 2SD774-34 Although he did not know what the differences were, the paperwork suggested using the latter which I ordered at 5.88 for two, Inc VAT and P&P.
  11. While waiting for the 2SDS774, I tried out some physically incompatible (size and/or lead configuration) transistors to further checkout the circuitry:
    1. I first bought some BC337. The best sample obtained (Outline specification Icmax=800mA, Pmax= 625mW and Gain =100 to 630 at 100mA) showed a curve tracer measured gain of 140 at 100mA reducing to 90 at 250mA (which was slightly better gain, and gain maintenance, than the first unbranded transistor) but it still struggled to get to the desired output voltage before exceeding its power rating.
    2. The best sample then obtained of a ZTX653 (Outline specification Icmax=2A, Pmax=1W & Minimum Gain =25 at 2A) showed a gain of 190 at 100mA only reducing to 170 at 250mA, but had a measured CJC of approximately 50pF. Despite the CJC, it worked well from a main oscillation point of view, but had a lower frequency (4 to 5 MHz) parasitic oscillation, which took a longer part of the main cycle to die out. Although I spent some time trying extra H.F.decoupling / shorting capacitors around the transformer feedback loop to eliminate this parasitic, this was not found to be possible. The higher gain of this transistor highlighted another feature of this design. As before, when the feedback winding first turns Q2 on, its collector voltage is falling but is still at a major fraction of the supply. The collector immediately goes into saturation and the current builds up rapidly in L2. The energy in the res onant transformer causes the primary voltage to continue following a sine wave until it goes negative, when the current in L2 starts to reduce and eventually reverse. This reverse current in the collector of Q2 is sustained by reverse transistor action that maintains the collector voltage at approximately zero (in reverse mode saturation). With this transistor, a further operational mode develops after the base feedback winding passes its positive peak and before the primary goes positive. During this phase, as the bias is increased, the collector voltage actually goes negative before going positive again, following the base voltage negative for an increasing part of the cycle. This mode significantly increases the RMS voltage on the primary and achieves the desired secondary voltage with less base bias. The parasitic oscillation is shorted out in the forward and reverse saturation and negative Vce phases, but again starts at the point where the primary winding voltage goes positive.
    3. I then tried a lower current trans istor, a ZTX450 with CJC of around 5pF, to see if this reduced the parasitic oscillation. The best sample obtained of it (Outline specification Icmax=1A, Pmax=1W, Gain=100 to 300 at 150mA) gave a gain of 125 at 100mA reducing to 90 at 250mA. The net result is a compromise in desired performance between that of "a" and "b" and a higher frequency, lower duration parasitic than "b".
    4. I was trying to source a ZTX694 (Outline specification Icmax=1A, Pmax=1W and Minimum Gain=400 at 200ma) because of its high gain and suspected low CJC wh en the samples of 2SD774 ar rived from Sony. These turned out to be in a somewhat larger (but space wise compatible) package than the original. They had a CJC of approximately 50pF instead of the expected 15pF and had identical, and exceptionally good, gain/linearity figures of 241 at 100mA only reducing to 233 at 250mA (and very well maintained to much larger currents than that). These performed slightly better than the ZTX653 from the basic operation point of view, but similar to it from a parasitic oscillation point of view. At th is stage I was able to confirm that this ringing is entirely due to the self-resonant frequency of L2, reduced in frequency by the collector base capacitance CJC of Q2. Adding extra collector to emitter (or collector to base) capacitance merely reduces the frequency of this parasitic and increases its duration, without affecting the main oscillation in any way. I should have noticed earlier that the collector is always positive and the base negative holding the transistor off when it occurs and saved myself worry about possible unreliability of the repair.
  12. The desired output voltages were generated for about 0.9mA injected Q2 base bias, resulting in 50mA power consumption. When the internal bias feedback loop was reinstated, the extra dissipation directly associated with it, plus the inefficiency involved in developing this power, caused the consumption to increase to around 61mA. In addition, this consumption further increased to around 68mA as the module PCB was slid into its case, presumably due to the can acting as a shorted turn on the EM field radiated by the transformer.
  13. It was noted that the bench PSU current limiting had to be set at a value higher than the steady state current consumption, to avoid the PSU tripping. This indicates that, even under normal circumstances, there is extra base bias, and extra collector current, involved in turn on surges (Icpeak=0.75A ??). Potentially, the 3.5mA of available base bias current, with the necessary high gain transistor, could allow the Q2 collector current to build up above wire bond and dissipation destructive limits, if it occurred at the wrong part of the main cycle if a high voltage across L2 lasts too long. Even if the base winding voltage is still negative at this point, and some current needs to be diverted to develop the required base voltage across R9, there could still be enough bias current left to cause a failure, if turn on at the wrong time occurs e.g. as a result of hunting in the bias feedback loop due to faulty C4 and C8 capacitors.
  14. With the replacement 2SD774 transistor having a gain of 233 at 250mA, requiring approximately 1mA base bias to generate the correct value +38V and -26V rails, the AC output signal was 22V p to p at 85kHz instead of the 11V p to p at 94kHz stated in the documentation. I suspect the 2:1 amplitude conflict may be due to a documentation error (e.g. if the output is used in differential rather than single ended mode or there was confusion between peak and peak to peak), but the frequency difference is slightly worrying, not knowing what this signal is used for and noting that there is a select on test inductor involved in the circuit which could affect the tank resonant frequency.